The present invention relates to memory devices, and more particularly to address selection circuitry having lower current consumption during an internal address selection operation.
Dynamic Random Access Memories (xe2x80x9cDRAMsxe2x80x9d) are commonly used in a variety of electronic devices, such as computers. A high level block diagram of a typical DRAM is shown in FIG. 1. The DRAM shown in FIG. 1 is a synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) 100, although the principles described herein are applicable to any memory device having a need for internal address selection circuitry. The SDRAM 100 includes an address register 104 that receives row addresses and column addresses on a multiplexed address bus. The address bus is generally coupled to a memory controller (not shown) which provides the row and column addresses.
Typically, a row address is initially received by the address register 104 and applied to a row address multiplexer 108. The row address multiplexer 108 couples the row address to a number of components associated with memory banks 130a-d, depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 130a-d is a respective row address latch/decoder 120a-d which stores the row address and applies various signals to its respective array 130a-d as a function of the stored row address. The row address multiplexer 108 also couples row addresses to the row address latches 120a-d for the purpose of refreshing the memory cells in the arrays 130a-d. The row addresses are generated for refresh purposes by a refresh counter 110. As will be described in greater detail below, the row address multiplexer 108 includes address selection circuitry 109 that selects between providing the external address received from the address register 104 and the address received from the refresh counter 110 to the row address latch/decoder 120a-d as an internal address.
After the row address has been applied to the address register 104 and stored in one of the row address latches/decoder 120a-d, a column address is applied to the address register 104. The address register 104 couples the column address to a column address latch 112 where the address is stored. Column decoders 124a-d receive the column addresses from the column address latch 112, and apply various signals to associated column circuitry 128 and respective sense amplifiers for the respective arrays 130a-d. Data to be read from the arrays 130a-d are coupled to the column circuitry 128 and subsequently coupled to a data output register 142, which applies the data to a data bus 150. Data to be written to one of the arrays 130a-d are coupled from the data bus 150 through a data input register 154 to the column circuitry 128, where the data are transferred to the arrays 130a-d. 
The above-described operation of the SDRAM 100 is controlled by control logic 102 responsive to high level command signals received on a control bus. These high level command signals, which are typically generated by a memory controller (not shown), often include a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the xe2x80x9c*xe2x80x9d designates the signal as active low. The control logic 102 generates a sequence of command signals responsive to the high level command signals to carry out various memory functions and program memory modes designated by each of the high level command signals, such as memory read, memory write, refresh operations, standby mode, and the like. For example, driving the RAS* and CAS* inputs low with CKE* high will cause the SDRAM 100 to enter a self-refresh mode. In the self-refresh mode, the control logic 102 causes the memory cells corresponding to the address provided by the refresh counter 110 in the arrays 120a-d to be periodically refreshed. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
As mentioned previously, in the memory device 100, the row address multiplexer 108 is commanded by the control logic 102 to provide as an internal row address to the row address latches/decoders 120a-d either an external address latched by the address register 104 or a CBR address provided by the refresh counter 110. Where the memory device 100 is operating in a normal mode, the row address multiplexer 108 provides the external address to the row address latches/decoders 120a-d for accessing the corresponding row of the memory arrays 120a-d. The CBR addresses, on the other hand, are provided by the refresh counter 110 to the row address latches/decoders 120a-d to facilitate auto-refresh and self-refresh operations, which are well known in the art.
FIG. 2 illustrates a known design of an address selector 200 that is included in the address selection circuitry 109. As illustrated in FIG. 2, the address selector 200 provides one bit of the row address that is provided to the row address latches/decoders 120a-d. Thus, the address selection circuitry 109 typically includes multiple address selectors 200 to provide appropriate number of bits of the row address to the row address latches/decoders 120a-d. The multiple address selectors 200 operate identically, and consequently, the description of the address selector 200 provided herein is applicable to the other address selectors as well.
The address selector 200 provides either the external address or the CBR address as the internal address to the row address latch/decoder 120 based on the row address activation signal ARA. Specifically, where the ARA signal is HIGH, the external address is provided, and where the ARA signal is LOW, the CBR address is provided instead. The generation of the ARA signal is typically performed by circuitry (not shown) under the command of the control logic 102 and in response to the mode of operation of the memory device 100.
As is commonly known in the art, the address bus of the memory device 100 is multiplexed between row and column addresses, consequently, the ARA signal is strobed to latch the row address before the column address becomes valid. Thus, after the external row address is latched by the row address latches/decoders 120a-d, the ARA signal returns to an inactive state, the multiplexer 202 switches to providing the CBR address as the internal address. In essence, the row address multiplexer 108 provides the CBR address to the row address latches/decoder 120a-d as a default when the ARA signal is not active.
It is generally accepted that it is more desirable to have lower power consuming devices, including in particular, memory devices. To this end, circuits included in devices have been designed to be more power efficient. From this perspective, the address selector 200 may not be a desirable alternative because its design includes inherent power inefficiencies.
An example of such inefficiencies will be discussed with respect to FIG. 3. As previously discussed, the address selector 200 provides the CBR address to the row address latches/decoders 120a-d as a default, or more specifically, when the ARA signal returns to an inactive state after latching an external row address. As shown in FIG. 3, at a time T0 a memory array access operation is initiated by activating a bank and row of memory. The ARA signal becomes active to set the multiplexer 202 (FIG. 2) to provide the clocked external row address as the internal address for activation of the row corresponding thereto. At a time T1, when the ARA signal becomes inactive after latching the external row address, the multiplexer is set to the default state and provides the CBR address to the row address latches/decoders. At a time T2, the ARA signal becomes active again to latch an external row address corresponding to the row of memory that is to be deactivated, thus, completing the memory array access operation. Consequently, the multiplexer 202 is again set to provide the external address to the row address latches/decoders 120a-d. When the ARA signal again becomes inactive at a time T3 following the latching of the external row address, the multiplexer 202 switches back to the default state of providing the CBR address as the internal address.
The power inefficiencies related to the address selector 200 result from the multiple transitions of the internal address that occur each time the ARA signal returns to an inactive state. It is well known that with CMOS circuitry, which is generally extensively incorporated in the design of integrated circuits, such as memory device 100 of FIG. 1, current is consumed or dissipated when transitions from one logic state to another occur. Where multiple circuits are involved, such as in the address selection circuitry of the row address multiplexer 108, buffer circuitry driving the internal address bus, and latch and decoder circuitry of the row address latches/decoders 120a-d, the cumulative current consumption during a logic transition may be significant. Thus, minimizing the number of unnecessary transitions the circuitry must make will generally reduce power consumption.
As illustrated in FIG. 3, the ARA signal is typically strobed twice in a memory access cycle, resulting in four transitions of the internal address. As mentioned previously, the transitions occurring at the times T1 and T3 merely result from the address selector 200 returning to the default state of providing the CBR address as the internal address, although the CBR address is not used during the memory access operation. Consequently, the transitions at the times T1 and T3 cause the address circuitry involved to unnecessarily consume current. In the worst case, the external row address latched while the ARA signal is strobed and the CBR address are complementary, causing all bits of the internal address to transition. Moreover, the current consumption of the memory device 100 having address selection circuitry 109 that includes the address selection circuit 200 becomes unpredictable because the quantity of current consumed as a result of transitions of the internal address is related to the particular external address latched and the particular CBR address provided by the refresh counter 110. As this changes frequently, it becomes difficult to accurately predict the power consumption of the memory device 100.
The present invention is directed to an address selection circuit and method that reduces current consumption by avoiding unnecessary transitions in an internal address signal. The address selection circuit includes a first transfer gate having an input to which a first address signal is applied and an output to which the input is coupled in response to an active first control signal applied to a control terminal of the first transfer gate. The address selection circuit further includes a second transfer gate having an input to which a second address signal is applied and an output to which the input is coupled in response to an active second control signal applied to a control terminal of the second transfer gate. A latch coupled to the outputs of the first and second transfer gates is also included in the address selection circuit to latch the either the first or second of the input address signals as the internal address. The latch maintains the logic level thereof even after the enable signal becomes inactive.